Arduino Vidor CAN bus support

Arduino have just announced a bunch of new boards, including one with an on board FPGA chip (plus a SAMD21 Cortex-M0+, plus an ESP32 WiFi and Bluetooth Module). A Field Programmable Gate Array (FPGA) chip is possibly the most impressive piece of electronics going. They are essentially a way of creating entirely custom digital electronic circuits (resistors and transistors) all inside a tiny chip, and completely reprogrammable – genius!

See more about the Arduino Vidor CAN bus support after the break.

One way of thinking about FPGAs is that they are a PCB inside a chip, which means signals have to be routed around internally, and electrical signals are not strictly digital, but actually are still analogue with a corresponding voltage and current. However, they provide a significantly higher density of components than even the smallest surface mounted discreet components would. Therefore, they can be used to implement very complex circuitry in a very small space, with the added bonus of being reprogrammable. Another benefit is that as they behave like electrical circuits, instead of a general purpose processing unit, they do not need to step through a program one instruction at a time. Instead, in one time step (or clock cycle) all of the ‘circuit’ on the chip is executed at the same time. Similar to a traditional analogue circuit, multiple signal paths, and multiple separate signals all ‘get processed’ (by physics) at the same time. The same is true on FPGAs, they are essentially an infinitely parallel execution device (limited to how much can fit on the chip). For these reasons, FPGAs are often used for processings significant amounts of data in parallel, required at high speeds. Video is a good example of this, but also a number of communication protocols. FPGAs are also a good way to reduce the number of components required in a design. It is essentially possible to emulate any discreet chip inside an FPGA. These emulated chips (or protocol implementations, alorithms, signal processing stages, etc.) are called IP (Intellectual Property). IP is an implementation within FPGA code to perform a certain function. A lot of these IP blocks are cross compatible across FPGAs, and can be implemented alongside other IP blocks and custom code with a single FPGA chip. Where the IP uses external pins these can generally be configured to use any of the general purpose IO pins on the device. This makes FPGAs extremely flexible and capable of behaving like other chips within your project.

So, theoretically, the new Arduino Visor is a very good candidate to provide CAN bus connectivity through the Altera (now Intel) Cyclone 10 LP series FPGA on board. This should be made possible by the CAN bus IP also available through Altera. However, on the CAN bus IP page, it does mention support for the Cyclone series chips, but only the Cyclone IV, Cyclone V, Cyclone V SoC

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